Timing Design Engineer (Back-End / STA)

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Job details

Company overview

The company is a semiconductor startup specializing in image processing and AI‑focused SoC and IP development. It provides end‑to‑end technical support covering planning, design, verification, and mass production, with an emphasis on performance optimization and reliability. Its solutions primarily target smart consumer products, with expansion into advanced industrial applications underway.

Responsibilities

Physical design and timing closure for SoCs.
Main responsibilities:

• Development and execution of timing closure strategies
• PPA optimization (Power, Performance, Area)
• SoC physical design flow management
• Static Timing Analysis (STA)
• Clock Tree Synthesis (CTS)
• Physical design vendor management
• Sign-off support

Requirements

Minimum requirements:

• Experience with STA tools (PrimeTime / Tempus, etc.)
• Understanding of SoC physical design flows
• Timing closure experience
• Experience with advanced process nodes

Preferred qualifications:

• Clock architecture design
• Low-power design methodologies (UPF: Unified Power Format)
• IR drop / EM analysis
• Experience with advanced TSMC processes

Salary

12 - 16 million yen

Location

Tokyo