Timing Design Engineer (Back-End / STA)

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募集要項

会社概要

業務内容

Physical design and timing closure for SoCs.
Main responsibilities:

• Development and execution of timing closure strategies
• PPA optimization (Power, Performance, Area)
• SoC physical design flow management
• Static Timing Analysis (STA)
• Clock Tree Synthesis (CTS)
• Physical design vendor management
• Sign-off support

応募条件

Minimum requirements:

• Experience with STA tools (PrimeTime / Tempus, etc.)
• Understanding of SoC physical design flows
• Timing closure experience
• Experience with advanced process nodes

Preferred qualifications:

• Clock architecture design
• Low-power design methodologies (UPF: Unified Power Format)
• IR drop / EM analysis
• Experience with advanced TSMC processes

給与

1200 - 1600 万円

勤務地

東京