Synthesis Engineer

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募集要項

会社概要

業務内容

• RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
• Design flow/methodology development and innovation for front-end design challenges.
• Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.

応募条件

• BCH and above in EE, CS related fields.
• 3-10 years working experience. Especially, experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification.
• Familiar with EDA CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
• Familiar with tcl/Perl/Python/C++ program.
• PPA improvement experience is a plus.
• Familiar with CPU architecture is a plus.
• Good command of Japanese. Fluent in English is a plus.

給与

800 - 1400 万円

勤務地

神奈川