Design Verification Engineer | 設計検証エンジニア

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募集要項

会社概要

業務内容

Main responsibilities:

• Verify the company's product
• Develop verification methodology and implement test bench components using System Verilog, UVM, and low power verification
• Develop comprehensive test plan and implement test cases to verify different test chips
• Work closely with Design and DFT teams to develop/verify various functional/DFT tests
• Write functional cover groups and cover points for coverage closure.
• Perform RTL code coverage, System Verilog Assertion coverage, and System Verilog functional coverage
• Drive and adopt new verification methodologies and flows for efficiency improvements.

応募条件

Minimum requirements:

• Education: BCH and above in EE, or CS related fields
• 3-15 years of hands-on experience in above fields
• Strong problem solving, debugging and programming skills (Python/TCL/C++)
• Strong hands-on experience with architecting and developing IP/SoC level reusable verification environments using SystemVerilog UVM methodologies.
• Hands-on experience developing testbench and testcases in System Verilog
• Knowledge in Constrained Random and Coverage Driven testbench  
• Gate Level Simulation experience
• Proficiency in English

給与

600 - 1000 万円

勤務地

横浜